An integrated circuit for driving a plasma display panel, which may be abbreviated to IC for driving PDP, consists of a high voltage output circuit portion that operates with a high voltage of 100 V or greater, and a logic circuit portion that operates with a voltage of about 5 V. The high voltage output circuit portion includes active elements such as n channel MOSFET or p channel MOSFET, and passive elements such as resistors. These elements constitute a one-bit output circuit portion, and such an output circuit portion is provided for each bit in a circuit for producing a multiplicity of bits of outputs.
In an integrated circuit having a plurality of high voltage devices that operate with 100 V or higher, a pn junction isolation structure using epitaxial wafer or self isolation structure has been employed for isolating the devices from each other. In the following description, "n" or "p" prefixed to regions or layers means that the regions or layers have electrons or holes, respectively, as majority carriers.
FIG. 3 is a cross sectional view of a known example of the pn junction isolation structure. A part of an n epitaxial layer 42 on a p substrate 41 is isolated from the other parts by a p.sup.+ embedded region 43 and a p.sup.+ isolation region 44 that has a depth large enough to reach the p.sup.+ embedded region 43, so as to provide an island-like n region 45. In this island-like n region 45, p base region 46, n source region 47, n.sup.+ embedded region 49, and n.sup.+ wall region 48 that has a depth enough to reach the n.sup.+ embedded region 49 are formed, as shown in FIG. 3. In addition, a gate electrode layer 51 is formed on a gate insulating film 50 over an exposed surface portion of the p base region 46, and a source electrode 52 is formed in contact with the surfaces of the p base region 46 and n source region 47, while a wall electrode 53 that provides a drain is formed in contact with the surface of the n.sup.+ wall region 48, so that an n channel MOSFET is formed.
By applying 0 V to a substrate electrode 55 formed on the p isolation region 44 and applying 100 V to the wall electrode 53, pn junction between the island-like n region 45 and p substrate 41 is reverse-biased, and the island-like n region 45 including the n.sup.+ wall region 48 is isolated due to the pn junction. The p isolation region 44 and n.sup.+ wall region 48 must be spaced from each other by at least about 20 .mu.gm. An output is taken out from the source electrode 52 formed on the n source region 47. This structure also includes high voltage field plate 56 and low voltage field plate 57 both of which serve to reduce an electric field on its surface. Although not illustrated in FIG. 3, a gate electrode consisting of a metal layer may be often formed in contact with the gate electrode layer 51.
In the structure as described above, the p base region 46, n epitaxial layer 42 and p substrate 41 constitute a parasitic transistor 58. In the case of the IC for driving PDP, in particular, the potential of the source electrode 52 becomes higher than that of the drain electrode 53 in a certain operating mode, and the parasitic transistor 58 may undesirably conduct in such a case. To solve this problem, a high concentration n.sup.+ embedded region 49 is provided for limiting parasitic current 59 of the parasitic transistor 58. Although the p base region 46, n epitaxial layer 42 and p isolation region 44 constitute another parasitic transistor, parasitic current of this parasitic transistor is limited by the n.sup.+ wall region 48 having a high impurity concentration.
FIG. 4 is a cross sectional view of a known example of the self isolation structure. A p source region 67 and a p drain region 66 are formed in an n well region 62 that is formed in a surface layer of a p substrate 61. In addition, a gate electrode layer 71 is formed on a gate insulating film 70 over the surface of the n well region 62, and a source electrode 73 is formed in contact with the surface of the p source region 67, while a drain electrode 72 is formed in contact with the surface of the p drain region 66. Thus, a MOSFET is provided. By applying 0 V to a substrate electrode 75 formed on the p substrate 61, and applying 100 V to the source electrode 73 formed on the p source region 67, an output is take out from the drain electrode 72 formed on the p drain region 66. This structure also includes p+substrate contact region 61a, n.sup.+ well contact region 62a, and p.sup.+ drain contact region 66a, each of which has a high impurity concentration.
Although the self isolation structure of FIG. 4 is available at a low manufacturing cost, the p drain region 66, n well region 62 and p substrate 61 tend to form a parasitic transistor 78, which undesirably produces a relatively large parasitic current 79. The pn junction isolation structure of FIG. 3, on the other hand, is manufactured at a relatively high cost, but is advantageous in reduced parasitic current 59 of the parasitic transistor 58 as described above.
FIG. 5 is a circuit diagram illustrating one example of IC for driving PDP, which is a push-pull circuit that is constructed to produce multiple-bit outputs. In this example, n channel FETs are connected in series between Vdd of 100 V and Vss of 0 V. Since the output varies in a range of 0 to 100 V, this circuit is constituted by high voltage devices having a withstand voltage of 1000 V or higher.
FIG. 6 is a cross sectional view showing a portion of an integrated circuit on the high voltage side thereof, which realizes the circuit of FIG. 5 (with three outputs in this case) using pn junction isolation. Individual semiconductor devices are formed in respective island-like n regions 85a, 85b, 85c that are isolated from each other by pn junction, and adjacent devices are separated from each other by a p.sup.+ embedded region 83 and a p isolation region 84. The isolation of the devices is achieved by applying a high voltage of 100 V or greater between the p isolation region 84 and an n.sup.+ wall region 88, and therefore a spacing of 20 ,m or larger, for example, is needed between these regions 84, 88 in each junction isolation portion, so that the device will not break down even with the high voltage applied thereto. With such a spacing provided for each device, the chip area is undesirably increased. Further, the pitch or interval between the adjacent devices cannot be reduced to such an extent as recently required in integrated circuits for producing multiple-bit outputs.